Towards a better understanding of FIB architectures
Today’s network switches are mostly black boxes, and there isn’t much, if any, information released about their inner workings. One part of each network switch is the database that contains entries for L2 (switches) and L3(routers) forwarding. From previous projects, it became clear that updates on those databases can be slow. While L2 databases are also of interest the main focus of the project will be the L3 database.
With this project, we would like to build a software model of such databases to better understand the dynamics at play. In particular why it takes so long to update entries. Luckily we won’t have to start completely from scratch and at least some of the algorithms that are used today are known. This article here: (Longest Prefix Matching in Networking Chips) gives quite a good overview of the approaches used in todays networking chips.
Milestones
- Building a representative FIB simulator
- Understanding if the slow updates stem from bandwidth limitation of the memory or if part of the bottleneck is the transformation of the entries into a format that can be written directly into the database?
- Find out if there are specific patterns of entries that use more space in the database or take longer to insert
- Come up with solutions that can mitigate those problems
Requirements
- Solid programming skills
- Knowledge about routing/forwarding and especially longest prefix matching
- Knowledge about hardware elements like SRAM, DRAM and TCAM is a benefit
Supervisors
